Speaker
Description
Previous attempts to integrate FPGA acceleration into GNU Radio have primarily focused on front-end processing. This abstract proposes a novel approach: extending FPGA acceleration to a block-centric model using non-SDR PCIe FPGAs, with an emphasis on SWAP-C (Size, Weight, Power, and Cost). The goal of this talk is to demonstrate a proof-of-concept for an FPGA-accelerated GNU Radio block.
This work originated from a semester-long master's project utilizing a NiteFury II M.2 Commercial Off-the-Shelf (COTS) FPGA. In this proof-of-concept, data is transferred from the host computer to the FPGA at x4 Gen2 PCIe speeds, processed through a 2:1 decimation filter, and then sent back to the host. This workflow demonstrates the feasibility of using low-cost FPGAs to accelerate processing anywhere within a GNU Radio flowgraph.
While integration with GNU Radio is ongoing at the time of submission, a solution will be presented at the talk. This work serves as a foundational discussion on the future of FPGA acceleration in GNU Radio, providing a framework adaptable from low-cost boards like the NiteFury II to high-end Versal FPGAs, though further design and exploration are needed for managing and deploying GNU Radio FPGA blocks.
| Talk Length | 15 Minutes |
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