Speaker
Description
In this talk we explore using GNU Radio and Verilator to rapidly and incrementally translate an existing flow graph into a form suitable for running in the Programmable Logic (PL) of an FPGA. Where typical FPGA toolchains take many minutes to produce a bitstream, Verilator allows us to swiftly translate our model into C++ sources that produce a cycle-accurate simulation. By integrating our Verilated model as a block directly into GNU Radio and using existing blocks as a test harness, we reduced our development cycle time from 10-30 minutes per code change to sub-second feedback. Further, by employing existing GNU Radio flow graphs as a reference implementation and comparing our results, we were able to validate algorithmic correctness before we shipped the code to the FPGA itself.
This work came from our research group's efforts to demonstrate a prototype SDR based on the Xilinx Zynq UltraScale FPGA using an Analog Devices Mixed Signal Frontend (MxFE). Specifically, in order to demonstrate the capabilities of the ZCU102 + AD9081 evaluation modules, we built a partial DVB-S2 modulation chain (QPSK encoder, physical layer framer, and pulse shaping filter) that successfully ran at 250 MSPS.
| Talk Length | 15 Minutes |
|---|---|
| Link to Open Source Code | https://github.com/coffee-and-telesense/ascendarc-sdr-sttr-poc/tree/main/grc-hdl |
| Acknowledge | Acknowledge In-Person |