21–25 Sept 2026
Talley Student Union
America/New_York timezone
GRCon26 Call for Participation is Now Open

FPGA Processing on USRP Radios Using the RFNoC Framework

22 Sept 2026, 13:00
2h
3285 (Talley Student Union)

3285

Talley Student Union

Workshop SDR Framework Development Workshop

Speakers

Mr Neel Pandeya (National Instruments) Jonathon Pendlum (National Instruments)

Description

This workshop provides a tutorial on the RFNoC framework, including a discussion on its design and capabilities, demonstrations of several practical examples, and a walk-through of implementing a user-defined RFNoC Block and integrating it into both UHD and GNU Radio. The RFNoC (RF Network-on-Chip) framework is the FPGA architecture used in USRP devices, specifically the E310, E312, E320, X300, X310, N300, N310, N320, N321, X410, X420, X440. The RFNoC framework enables users to program the USRP FPGA, and facilitates the integration of custom FPGA-based algorithms into the signal processing chain of the USRP radio. Users can create modular, FPGA-accelerated SDR applications by chaining multiple RFNoC blocks together and integrating them into both C++ and Python programs using the UHD API, and into GNU Radio flowgraphs. Attendees should gain a practical understanding of how to use the RFNoC framework to implement custom FPGA processing on the USRP radio platform.

Talk Length N/A
Link to Open Source Code https://kb.ettus.com/Workshop_Tutorial
Acknowledge Acknowledge In-Person

Authors

Mr Neel Pandeya (National Instruments) Jonathon Pendlum (National Instruments)

Presentation materials

There are no materials yet.