GNU Radio Conference 2026

Your Flowgraph Is the Chip: GNU Radio Compiled Straight to Silicon

23 Sept 2026, 11:15

30m

Mountain Ballroom (Talley Student Union)

Paper (with talk) Heterogeneous signal processing frameworks Main Track

Speaker

Charles McClish

Description

Kyttar is a chip you program by drawing a flowgraph. It is a homogeneous array of small asynchronous compute cells, and a GNU Radio flowgraph maps onto it directly: a block becomes a region of cells, and a connection becomes a route between them. The graph you draw in GNU Radio Companion is essentially the layout of the design on the silicon, so there is no separate hardware-design step to manage. placeKYT is the open-source tool that does the mapping. It reads a flowgraph, places and routes it onto the array, runs it, and sends the output back into GNU Radio through custom source and sink blocks, so from the outside it looks like ordinary GNU Radio.

The harder problem is the block library. Every Kyttar block so far has been written by an AI agent. The placeKYT source includes the block-generation workflow: the prompts, the rules an agent follows to lay a block out across cells, and testbenches that check each generated block against its GNU Radio equivalent. A running knowledge base captures what works as blocks are built, so lessons learned on one carry into the next. Running unattended, the workflow has produced and verified nine feed-forward blocks, including configurable FIR filters and an NCO, and measured each block's quantization noise against its GNU Radio floating-point original. The agent also builds multicell blocks that place automatically and adapt their shape to fit the array.

Because a design runs as cells rather than a compiled netlist or an FPGA bitstream, you can watch it work: set breakpoints, single-step the running design, and inspect any cell while the array executes. Debugging means seeing what the hardware actually does, not inferring it from a waveform.

This runs today on simKYT, a free, cycle-accurate model of the chip. A 120-cell prototype is in fabrication, with first silicon expected mid-November 2026, and the workflow does not change when it arrives. If it runs in the simulator, it runs on the board.