Last summer's USRP Hardware Driver (UHD) 4.0 release included a major overhaul of the RF Network-on-a-Chip (RFNoC) processing framework that enables high-throughput digital signal processing (DSP) on NI/Ettus Research's Universal Software Radio Peripheral (USRP) products. This architecture allows users to define algorithms to be performed by connecting DSP elements, or RFNoC blocks, together in a flowgraph that runs within the FPGA on the USRP. UHD provides the user with the tools to configure RFNoC flowgraphs and upload them to the USRP, but did you know that UHD also ships with several highly performant RFNoC blocks implementing popular DSP operations, battle-tested and ready for use in your applications?
In this talk, I'll spotlight the RFNoC blocks that ship with the UHD driver and describe their capabilities and available options. I'll also discuss different techniques for deploying the blocks within the RFNoC flowgraph that exploit the flexibility of the architecture and afford designers the utmost in software and hardware flexibility.
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