The RF Network-on-Chip (RFNoC™) is an open source framework from Ettus that allows for convenient development access to the field-programmable gate array (FPGA). The RFNoC framework therefore lowers the barrier to entry to develop FPGA based digital signal processing (DSP) blocks that can be used with UHD and GNURadio (Ettus, 2020). By utilizing the floor space available on the FPGA of select radio models, DSP can be done in hardware before the data is ever streamed to the host computer. This type of heterogeneous processing can increase the speed of computationally intensive algorithms by helping to parallelize operations on the FPGA prior to generalized processing on the host computer. In addition to computational savings, deploying algorithms to the FPGA can reduce latency by removing the need to send data to the host computer or by reducing the amount of data that needs to be streamed to and processed by the host computer.
This presentation and the accompanying paper discuss the lessons learned from RFNoC development on the Ettus X310 radio. We will describe the framework and implementation architectures that reduced development time and enabled complex algorithms to be run in real-time. The AXI-Stream Payload Context interface was selected for the development of the processing blocks. A brief overview of this interface is discussed along with methods for sending block-generated packets.
The blocks that are presented in this work are for the implementation of fast spectrum sensing (FSS) (Kirk et al., 2018) for dynamic spectrum sharing applications. FSS operates by taking a sample of the spectrum and then looks for the largest band that is unoccupied by the primary users and can utilized by the radio's application. Due to the time-frequency agility of modern communications networks, the radio must be able to sense a new primary user in sub millisecond timescales in order to minimize interference. We will demonstrate two different detection methods for checking for a signal in each frequency bin of an FFT frame. As previously mentioned, FSS is a speed critical application, as a new emitter could begin transmitting at any time and the system would need to jump out of the way and select a new sub-band. Because of this the FSS algorithm needs to be implemented in the FPGA to minimize processing time and reduce streaming data and latency requirements to and from the computer. Minimizing the processing and data requirements ensures that the system can run the algorithm on each frame of data as quickly as possible such that a transmit waveform selection algorithm always has the most recent spectrum estimate.
A block architecture is presented for two versions of the FSS algorithm. The first allows for the implementation of a simpler algorithm with a predetermined threshold, that only needs to see each sample once and allows data to continue through the passthrough port of the block uninterrupted. The second architecture discussed enables a more robust algorithm that needs to calculate the threshold before it is applied. This is accomplished through caching of packets to allow for the data to be accessed or iterated over multiple times by the algorithm. Much of the input and output timing complexity usually associated with developing streaming FPGA IP is shouldered by RFNoC which allows for a more singular focus on the algorithm implementation. Issues that were encountered with these implementations within this framework will be described and the throughput and bandwidth performance will be discussed and demonstrated.
This work was sponsored by the Defense Advanced Research Projects Agency (DARPA) under grant HR0011-20-1-0007. The views expressed in this article are those of the authors and do not reflect official policy or position of DARPA, or the U.S. Government, No official endorsement by DARPA should be inferred. Approved for public release; distribution is unlimited.
RF Network-On-Chip (RFNOC™) Specification. Ettus Research, 2020. Rev. 1.0
Kirk, B. H., Narayanan, R. M., Gallagher, K. A., Martone, A. F., and Sherbondy, K. D. Avoidance of Time-Varying Radio Frequency Interference with Software-Defined Cognitive Radar. IEEE Transactions on Aerospace and Electronic Systems, (4):1090-1107, November 2018. doi:10.1109
|Secondary Topic||Wireless Spectrum Management|